VITAL——A VHDL INITIATE FOR ASIC MODEL DESIGN

VITAL (VHDL Initiate Towards ASIC Library) is a new IEEE standard of VHDL initiate for building ASIC models. It supports a description specification and standard packages: Timing Package and Primitive Package, for designer to build the ASIC model, to design a circuit conveniently and formally. This paper introduces the basic contents and the approach to describe circuit models by using VITAL.