Macro Model for Estimating Maximum Power of CMOS Circuits

Based on the achievements of macro model for mean power of register transfer level (RTL) circuits, this paper models maximum power of circuits as a function of the pattern pair sequence length and transition density, then uses neural networks to fit the maximum power function. Experimental results on ISCAS85 benchmarks demonstrate that the discrepancy between computed values of macro model and simulated results can be limited to 10%.