Reducing Power Dissipation During Delay Test Application
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Abstract
Re-ordering the test-pairs in the test sequences is introduced to minimize the switching activity of the circuit-under-test during test application.Hamming distance between test-pairs is used to guide their re-ordering. This guarantees a decrease in power dissipation without reducing the delay fault coverage.Experimental results are presented to demonstrate a 90% average reduction of the circuit activity for the test application.
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