Logic Path Sizing Optimization Using Extended Logical Effort

Path delay optimization in awareness of interconnect wire has become an important issue in VLSI physical design process. An Extended Logical Effort (ELE) that characterizes total delay of logical gate and interconnect wire load,as well as an ELE based path sizing optimization flow,are proposed. Parameters from LE are maintained in ELE and interconnect parameters are fully supported by back-end RC extraction flow. Given delay distribution strategy parameters and total effort delay value,this optimization flow can generate both optimal logical gate sizes and interconnect wire lengths in just one calculation pass without iteration. Dynamic programming is used to limit the solutions of every stage to those that satisfy both physical and technology constraints. Compared with the existing method,the proposed flow meets various target delay requirements,and results in shorter total wire length and smaller area with fewer computing resources.