A Novel Approach to Fast Simulate Maximum Power Dissipation of CMOS Combinational Circuits

High peak power makes VLSI circuits suffer from great instantaneous current and severe electro-migration，which may lower chip’s reliability and performance．Thus it is very imperative to estimate effectively accurate peak power dissipation of circuits．Because it has to take long time to compute power dissipation of CMOS circuits with delay，it needs extensive CPU time to simulate the maximum power consumption of circuits．In order to get an efficient estimation of the peak dissipation of CMOS combinational circuits in a tolerable period，this paper proposes a novel hierarchical approach．Experiments with the ISCAS85benchmark circuits demonstrate that this approach saves much more time and can give an accurate estimation of peak power dissipation．