Deterministic and Low Power BIST Based on Scan Patterns Partition

Various LFSR reseeding methods have been proposed to improve fault coverage in traditional pseudo-random BIST and at the same time yield good test data compression. But a drawback of these methods is that the unspecified bits are filled with random values resulting in a great deal of transitions during scan-in thereby causing high power dissipation. In this paper, we present a new deterministic pattern generation structure that can be used in conjunction with LFSR reseeding scheme. The proposed scheme utilizes scan slices overlapping of test patterns to reduce the number of specified bits and the number of transitions at the same time. As a result, the scheme can significantly reduce test power and even further reduce test storage. A decoder is used to generate control signals. Experimental results indicate that the proposed method significantly reduces the switching activity by 80% and only needs a relatively small test data storage(25% of original Mintest test sets).