METHOD TO CREATE VHDL SIMULATION MODEL FOR TECHNOLOGY CELLS IN HIGH LEVEL SYNTHESIS

This paper discusses the necessity and method to create the delay model，area model and their VHDL simulation model library for technology cells in the realization of HLS／BIT （High Level Synthesis ／ Beijing Institute of Technology） system．The VHDL model can be embedded to most VHDL simulators to realize post-simulation which is related to technology．It is useful to users of high level synthesizer and can be used in a larger area．