A H.264 VBSME SAD Algorithm and Architecture for Hardware Optimization

The hardware performance of H.264 macroblock-parallel VBSME SAD structure is discussed,and a novel pixel smoothing and resampling algorithm is proposed for hardware optimization.In this SAD algorithm,the current and reference pixels are partitioned into 2×2 subblocks,then smoothed and resampled for seven variable-block-size SAD calculations.It can effectively decrease the depth and width of cascaded adder for hardware reduction.Experimental results show that the proposed algorithm and its architecture can save over 53% hardware and power cost but only causes less than 1% RDO loss.It is very suitable for high-parallelism H.264 VLSI solutions due to its excellent hardware performance.