Implementation of A Verilog-VHDL Translator

Hu Yanxiang, Liu Mingye. Implementation of A Verilog-VHDL TranslatorJ. Journal of Computer-Aided Design & Computer Graphics, 2004, 16(8): 1074-1079.

Citation:

Hu Yanxiang, Liu Mingye. Implementation of A Verilog-VHDL TranslatorJ. Journal of Computer-Aided Design & Computer Graphics, 2004, 16(8): 1074-1079.

Citation:

Hu Yanxiang, Liu Mingye. Implementation of A Verilog-VHDL TranslatorJ. Journal of Computer-Aided Design & Computer Graphics, 2004, 16(8): 1074-1079.

Abstract

Based on uniformed timing model and design reference hierarchy,semantics-directed method is used in translating Verilog description to VHDL.By decomposing and reconstructing the parsing result,transferable subsets are enlarged and limitations on writing style are reduced while keeping the design functionality identical and synthesizable.Some typical examples of translation are illustrated.

FullText(HTML)

Turn off MathJax

Article Contents

Export File