A Routability Driven Packing Algorithm for FPGA

In this paper, a packing algorithm based on routability is proposed. This method begins with selecting logic element (LE) with minimum connectivity factor as the seed of the packing, and then uses a heuristic function based on routability-driven to obtain the most appropriate LE to pack into the configurable logic block (CLB). The number of the used pins of the CLB and the inter-CLB wires can be reduced simultaneously. Both number of nets and routing tracks have been improved about 30% when compared with previous algorithms. The time complexity of this algorithm is still linear.