Automatic Gate-Array Design for ASIC

In this paper, the characteristics of gate array design is elaborated from the development of IC's CAD/CAM. For the design of a specific circuit, the procedure of gate array automatic design which involves schematic entry, simulation, time verification, automatic placement and routing, as well as layout data generation and its conversion has been developed systematically. The basic idea and the way have been given, in which the base slice and macrocell library of gate array are established and described. Thus, the process of gate array automatic design is formed. All database files in each step are classified in detail. Logic diagram and waveform output and layout that realizes physically logic schematics for the circuit are supplied.