Component Partition of VHDL Sequential Statements and Generation of Abstract Circuit Structure

The paper discusses the standard of syntax and semantics of VHDL sequential statements in the register transfer level (RTL) synthesizable design along with templates of logic function, storage, and gateway components in these statements. The author presents the algorithm of building construction tree of if, case and Assignment statements. The algorithm of format discriminance, component partition and generation of abstract circuit structure, based on the statement construction tree are demonstrated.