Optimize Asynchronous Design by Synchronous Synthesis Tool

The existing synchronous tools’direct mapping synthesis methods for bundled-data asynchronous circuit can’t constrain timing effectively.The block by block synthesis can’t achieve global optimization.Additionally,the standard-cells-composed C-elements decrease the performance and increase the size.Treated as a synchronous datapath,the4phase bundled-data pipeline can be compiled top-down and with timing constraints.The ful-l custom C-elements are used in it and regarded as combinatorial gates during timing analysis.Circuit synthesized using this methodology will be better.A data-flow AES chip was implemented with this method.Its datapath area-delay product is about88％ of the result by direct mapping methods.The fabricated circuit’s entire performance is higher than that of a Balsa-synthesized AES circuit.