A CYCLE-BASED ALGORITHM FOR VHDL SIMULATOR

Cycle-based algorithm is implemented to raise the speed of VHDL simulator．It gains high performance through the ignorance of timing information within a cycle．But it is confined to synchronous description．Event-driven simulation engine and cycle-based simulation engine have been imbedded in the same simulation environment and can be used to asynchronous description and synchronous description respectively．Thus the simulation performance is improved without losing the flexibility of event-driven algorithm．