STATIC AND DYNAMIC ACCELERATED TECHNIQUES IN FAULT SIMULATION METHODS

Abstract To counter the most expensive stem fault simulation in fault simulation, this paper presents several accelerated techniques. Owing to these techniques, the area for stem fault simulation and the stems needed for fault simulation are all reduced greatly, so that the entire fault simulation time is decreased substantially. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency. Especially with the increase of circuit gates, its effectiveness improves obviously.