A Survey on Transaction Level Modeling for System-on-Chip Design

As the complexity of integrated circuit increases dramatically,the transaction level modeling （TLM） paradigm becomes a new research area in System-on-Chip （SoC） design. This paper presents a comprehensive survey of the researches and developments of TLM in recent years,including the involved key issues the efforts and advantages of TLM in modeling,simulation and verification. Besides the challenges,open issues and future perspectives are also highlighted.