Hierarchical Power Management Method hor IP-Based Design

When scaling down into deep sub-micron process, power consumption becomes one of the critical issues in modern VLSI circuit designs. Improved integration technique provides the possibility of multiple complex functions to work harmoniously on a single chip, which makes it necessary to efficiently manage the power dissipated by different components of the whole system. Based on the research of existing low power technologies and dynamic power management strategies in different design levels, a new hierarchical power management tactic and its implementation method are proposed for intelligent property based (IP-based) designs, which is very suitable for very large-scale systems with very good flexibility. The method provides an efficient design methodology aiming at reducing power consumption of electronic systems by performing selective shutdown of idle system resources. We applied the method to a very complicated SoC design in a scale of several millions gates and the experimental results prove that this method could achieve high ability of power management and reduce system power very greatly with no significant area and performance penalty on the chip.