Wang Wei, Han Yinhe, Hu Yu, Li Xiaowei, Zhang Yousheng. Wrapper Design for Low Cost and Low Power in SoC TestJ. Journal of Computer-Aided Design & Computer Graphics, 2006, 18(9): 1397-1402.
Citation:
Wang Wei, Han Yinhe, Hu Yu, Li Xiaowei, Zhang Yousheng. Wrapper Design for Low Cost and Low Power in SoC TestJ. Journal of Computer-Aided Design & Computer Graphics, 2006, 18(9): 1397-1402.
Wang Wei, Han Yinhe, Hu Yu, Li Xiaowei, Zhang Yousheng. Wrapper Design for Low Cost and Low Power in SoC TestJ. Journal of Computer-Aided Design & Computer Graphics, 2006, 18(9): 1397-1402.
Citation:
Wang Wei, Han Yinhe, Hu Yu, Li Xiaowei, Zhang Yousheng. Wrapper Design for Low Cost and Low Power in SoC TestJ. Journal of Computer-Aided Design & Computer Graphics, 2006, 18(9): 1397-1402.
Wrapper Design for Low Cost and Low Power in SoC Test
A novel parallel core wrapper design (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns.In order to achieve good shift time reduction from overlapping in pCWD,a two-phase process:"partition" and "fill",is presented.Experimental results on d695 of ITC2002benchmark demonstrate that about 50% shift time and 95% test power reduction can be achieved.
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