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YE Yizheng, CENG Xianjun, ZHANG Yan. REDUCING THE LOGIC-LEVEL OF THE COMBINATIONAL CIRCUITSJ. Journal of Computer-Aided Design & Computer Graphics, 1997, 9(1): 46-52.
Citation: YE Yizheng, CENG Xianjun, ZHANG Yan. REDUCING THE LOGIC-LEVEL OF THE COMBINATIONAL CIRCUITSJ. Journal of Computer-Aided Design & Computer Graphics, 1997, 9(1): 46-52.
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REDUCING THE LOGIC-LEVEL OF THE COMBINATIONAL CIRCUITS

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  • Abstract This paper discusses the boolean functions factoring method to minimize the logic-level of the combinational circuits and presents an algorithm to reduce the logic- level of the combinational circuits based on the Lawler clustering algorithm and the sublogic structural transformations.
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