VLSI Implementation of High-Performance QC-LDPC Decoder

Based on the rearranged Min-Sum decoding algorithm, a high speed partially parallel decoder architecture suited for quasi-cyclic low density parity-check (QC-LDPC) codes is proposed. A log-barrel-shifter is designed to reduce complexity of interconnection. By introducing micro-code-instruction, the decoder becomes independent with certain code rate and its regularity. It can also support any code rate without any changes in hardware. To adaptively control the power consumption under different channel conditions, a dynamic power control unit is adopted. Based on proposed decoder architecture, a QC-LDPC decoder for Chinese digital television?multi-media broadcasting (DTMB) standard (GB20600—2006) system is implemented based on SMIC 0.18 μm process, its frequency can be reached up to 100 MHz at the cost of 620 k gates.