An Overview of Power Optimization in High Level Synthesis

Power aware algorithms and recent researches in high-level synthesis procedure are reported in this paper.With the rapid development of IC technology,power consumption of circuits has surpassed the delay or area to become the most important design concern in IC design automation.It is noted that different design level will cause different potential for power saving,thereby it is necessary to optimize and minimize the power dissipation in the high-level synthesis. In this paper,the typical algorithms in the field are described systematically,and their basic principles are also analyzed and summarized.