Prescribed Skew Clock Routing Algorithm with Local Topology Optimization

This paper proposes a new algorithm for prescribed skew clock routing. It employs a novel merging strategy in conjunction with local topology optimizations for merging pairs and buffer insertions. Given prescribed skew constraints, nodes with larger delay target will first be considered and located at the bottom levels of the clock tree, an effective step to prevent detour wires. Experimental results show that the proposed algorithm can largely reduce total wire and buffer capacitance during clock routing, for the benchmark circuits that have been optimized by clock skew scheduling.