Formal Verification for Hardware Design and Temporal Logic

Han Jungang. Formal Verification for Hardware Design and Temporal LogicJ. Journal of Computer-Aided Design & Computer Graphics, 1990, 2(1): 1-6.

Citation:

Han Jungang. Formal Verification for Hardware Design and Temporal LogicJ. Journal of Computer-Aided Design & Computer Graphics, 1990, 2(1): 1-6.

Citation:

Han Jungang. Formal Verification for Hardware Design and Temporal LogicJ. Journal of Computer-Aided Design & Computer Graphics, 1990, 2(1): 1-6.

Abstract

This paper introduces the formal verification techniques for hardware designs using HOL (Higher-Order Logic) system. The implementation of a temporal logic in top level of HOL is described, and an example of verifying a latch using this mechanized temporal logic is given.

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