Transistor-Level Delay Simulation Methodology for VLSI Analysis

A novel transistor-level delay simulation method for nanometer technologies is proposed.It takes into account the short-circuit current,the input-output coupling capacitance,and the carrier velocity saturation effects of nanometer technology.The traditional Alpha-Power-Law MOSFET model is modified to accurately compute the channel current for today’s transistor analysis,and the modified nodal analysis （MNA） equation is used to compute output waveforms for gate delay and transition time.When a transistor in a gate is subject to one parameter change such as channel width,length,or threshold voltage V_T0, our simulation method can fast compute output waveform of the gate.HSPICE of BSIM370nm technology is used to verify the accuracy of our simulation method.Experimental results show that our method only takes 1.0ms per gate with only 5.04％（maximum） and 2.68％（average） accuracy loss on delay.