PLACEMENT WITH TIME CONSTRAINTS FOR FPGA DESIGN

Because of the resistance of CMOS configerable switches，SRAM-based FPGA has long delay on the connecting lines between CLB（IOB） s．Usually designers have to make some constraints on the delay of some paths．For example，the difference of delays between any two of a group of paths or the delays of some critical paths must be less than some determined value．In this paper，a FPGA placement algorithm，which can consider time constraints，is proposed．Instead of treating time constraints as part of the cost function，they are used to orientate the direction of simulated annealing，with the cost function only considering performance and routibility．Our model for path delay estimation is a good trade-off between accuracy and algorithm complexity．