An At-Speed Scan Test Scheme Using On-Chip PLL

At-speed test,which is efficient in detecting timing related faults,has been widely used in VLSI test.For at-speed test,one key issue is how to generate test clock at system speed.This paper presents an on-chip PLL （phase-locked-loop） based at-speed scan test scheme.In this method,an ATE （automation test equipment） clock is used during shift phase.On-chip PLL is used to generate at-speed clock during launch and capture phase.Therefore,at-speed scan test can be conducted with a low speed ATE.Experimental results on an AC’97controller circuit have verified the effectiveness of the proposed scheme.