Abstract: In this paper, based on the build-in self-test for logic circuits, a new approach is proposed to reduce pseudorandom test sequence length. After finding the faults detected hard in the circuit and creating their circuit models, the output signals of these models will be compressed by linear back shift register. By analyzing compact signatures the test sequence lengthes for the faults detected hard can be got. Final,using the relation between input probabilities and test sequence lengthes,a new approach is proposed to reduce the test sequence lengthes, and optimum input probabilities and shortest test sequence length are obtained.