Abstract: Register-Transfer Level Mapping (RTLM) algorithm for technology mapping at RT level is presented, which supports current day design methodologies using high-level design and design reuse. The mapping rules implement a source ALU using target ALU. The source ALUs and target ALUs were all represented by the general ALUs and the mapping rules were applied in the algorithm. The mapping rules were described in a table form. The mapping algorithm is well suited for mapping of regularly structured data path. Comparisons were made between the experimental results generated by 1-greedy algorithm and k-greedy algorithm, showing the feasibility of presented algorithm.