针对多时钟扫描测试的可测性设计方法
Design-for-Test Methodology for Multi-Clock Scan Test
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摘要: 在数字集成电路设计和生产中,基于扫描的测试方法是重要的可测性设计(design-for-test)技术.在多时钟的扫描测试设计中,不同时钟域之间信号的交叉会增加测试矢量的数目,从而增加了测试的成本.采用新的可测性设计方法,在扫描测试时用多路选通器隔断时钟域之间的交叉信号,使得原来处于不同捕获时钟组的时钟被分配到相同的时钟组中,在故障覆盖率基本不变的同时,减少测试矢量,降低测试成本.经实验验证,文中新的可测性设计方法可以明显地减少测试矢量数目,而且便于在RTL级加入.Abstract: In designing multi-clock scan test,the cross of signals from one clock domain to another will increase the number of test patterns and cost of testing.In order to improve the design-for-test the cross signals in different clock domains are blocked using multiplexers at scan test mode.Clocks belonging to different capture groups are placed in the same group,so the number of test patterns and cost of testing are reduced. Meanwhile,the fault coverage can be maintained almost the same.Experiments prove that the method described is efficient and can be easily implemented at RTL level.
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