Abstract: This paper presents a procedure of technology mapping based on a given standard cells library. The proccdure realizes the technology mapping by a series of logic structure's transformation followed by matching the standard cells with logic functions. It has a good tradeoff of delay time and area of delay time and area for special circuits. The procedure has been realized with C on the sun-4/SPARC workstation. The experiments show that the procedure has good complexity of running time and memory. it can handle the thchnology mappping of very large scale digital synchronous circuits(&=5000 gates), and it has hetter asults for combinational circuits.