Abstract: One of major concerns in physical design of deep-submicron VLSI circuits is to minimize the influence of crosstalk which will affect the chip's performance significantly if the designer does not pay attention to it in the phase of detailed routing. By studying how crosstalk is varying when adjusting wire's segment and space between neighboring wires, an optimization algorithm aimed at minimizing crosstalks by wire perturbation and space compression is developed in this paper. Computer simulation results show that the algorithm is effective in significantly decreasing chip's crosstalk. It is expected that the algorithm is applicable in the case of irregular routing areas.