SoC设计中的扫描测试技术

Scan Testing Technology for SoC Designs

摘要: 针对SoC的基于IP设计、多时钟域、多用异步逻辑、时钟门控、系统集成等特点,给出了一种层次化的扫描测试结构,并将该方法成功应用于一款具有数百万门级的SoC设计中.实验结果表明,该方法不但可以极大程度地提高芯片的可测试性,保证其测试覆盖率,也节约了产品开发时间和开发成本.

Abstract: In this paper, a hierarchical scan testing architecture is discussed and implemented in a multi-million gates scale SoC design successfully, and the experimental results show that the method not only improves the testability and assures the test coverage of the chip greatly, but also saves the development time and cost at the same time.