针对一种多模式逻辑单元结构FPGA的工艺映射

Technology Mapping for FPGA with Multi-mode Logic Cell

摘要: 结合FPGA设计的特点,提出一种可灵活配置的多模式FPGA逻辑单元结构及对其进行工艺映射的工具VMAP.该工具中除了采用一般的工艺映射算法外,还结合逻辑单元结构特点提出了专门的合并优化算法.该算法基于图的最大基数匹配,将部分查找表进行合并,减小了映射结果的面积开销.实验结果表明,对于标准的测试电路,结合文中的逻辑单元结构和合并算法得到的工艺映射结果平均可以减少15.7%的基本逻辑单元使用个数.

Abstract: A multi-mode FPGA logic cell and a technology mapping tool VMAP are presented.VMAP is composed of technology mapping for 4-input look-up tables(LUTs) and merging for multi-mode logic cells.The algorithm of merging is based on maximum cardinality matching and can merge some LUTs.Experimental results on MCNC benchmark circuits show that the number of LCs can be reduced by 15.7% on average after merging some LUTs into multi-mode LCs.