高级综合中工艺单元VHDL模拟模型的建立方法

METHOD TO CREATE VHDL SIMULATION MODEL FOR TECHNOLOGY CELLS IN HIGH LEVEL SYNTHESIS

摘要: 针对在实现HLS/BIT(High Level Synthesis/Beijing Institute of Technology,北京理工大学高级综合)系统时,需建立工艺单元的延时模型、面积模型及其VHDL模拟模型库进行讨论,并给出建立上述诸模型的方法.用此方法建立的VHDL模型可嵌入到大多数VHDL模拟器,从而实现工艺相关的"后模拟",这对高级综合器的使用者十分有用.因此,本方法具有一定普遍意义.

Abstract: This paper discusses the necessity and method to create the delay model，area model and their VHDL simulation model library for technology cells in the realization of HLS／BIT （High Level Synthesis ／ Beijing Institute of Technology） system．The VHDL model can be embedded to most VHDL simulators to realize post-simulation which is related to technology．It is useful to users of high level synthesizer and can be used in a larger area．