Abstract: A new structure D-Flip-Flop and corresponding scan Flip-Flop, namely Self-Adaptive D-Flip-Flop (SA-DFF) is proposed to reduce the power consumption of CMOS VLSI in normal operation mode and scan test mode simultaneously. SA-DFF compares the logic level of D-port and Q-port, automatically deactivates the internal clock when they are equal, or reactivates the internal clock when they are not equal. Under low data-transition probability circumstances, the SA-DFF consumes less power than a conventional one. In comparison with DL-DFF and gated clock, the main features of SA-DFF are capable of reducing both normal operation and scan test power dissipation without the need of extra pulse generation or glitch elimination circuits.