Verilog-VHDL翻译器设计与实现

Implementation of A Verilog-VHDL Translator

摘要: 在对Verilog和V HDL两种语言进行全面分析比较的基础上,依据统一的模拟时序模型和设计引用层次,采用模拟语义制导的方法完成从Verilog描述向VHDL描述的翻译转换.在保持功能等价和可综合性的同时,减少对语法和描述风格的限制.最后给出一些典型翻译实例.

Abstract: Based on uniformed timing model and design reference hierarchy,semantics-directed method is used in translating Verilog description to VHDL.By decomposing and reconstructing the parsing result,transferable subsets are enlarged and limitations on writing style are reduced while keeping the design functionality identical and synthesizable.Some typical examples of translation are illustrated.