Abstract: A novel constraint logic programming（CLP) based method of automatic simulation vector generation for RTL datapath is presented to reduce the design complexity by program slicing and generate CLP constraints based on bitvector arithmetic for the reduced design.It utilizes GProlog to solve the CLP constraints for producing simulation vectors.The method can generate uniform constraints with quick solution and generating complete vectors to satisfy the needs of simulation.Experimental results show that this approach is efficient and automated in generating simulation vectors for RTL datapath.