Abstract: This paper describes a deterministic test generation algorithm-DALG -EX18for MOS circuits with incomplete scan structure. This algorithm considers features of the circuits with incomplete scan structure, and also problems caused by high impedance state in MOS circuits. In the algorithm, 18-value D-calculus and new processing procedures are developed on the basis of traditional 5-valued D-algorithm. Additionally, testability measure is used to guide a d-drive and a consistency. Test generation, thus, can be speeded up and fault coverage can be rised. C program of this algorithm is implemented on VAX 11/ 750 and running results for some circuits are shown in the paper.