Abstract: The VLSL technology has advanced profoundly in recent years,and strong support is urgently required in this field from high performance IC CAD tools, or electrical design automation (EDA) software environment. Floorplanning and placement play a key role in physical design. The VLSI and ULSI design are under the deep submicron and very deep submicron technology today. The results of placement directly influence the physical design entirely. So the problem becomes a hot research subject. In this paper, the methods to be studied in topological representation of placement are analyzed in detail, and the progress of research in the field is introduced.