Abstract: A VLSI architecture for RTL synthesis is proposed,which needs three RAMs to construct the three lists.It builds up the parallel execution mode of input data and initializing lists simultaneously.A controller for the three list scanning and refining,and its finite state machine are also given.The operation flow is given by formal description.Finally,the hardware model of three dimensional set partitioning in hierarchical trees （3D SPIHT） is synthesized and simulated.Experimental results show that the design method is correct and effective.It can work with 59MHz frequency on FPGA and meets the real time needs of video encoder.