Abstract: A lifting-based architecture that considers coherence and resource reuse between DWT and entropy-coding unit with pipelining between them is introduced.The architecture shows higher stable speed and better flexibility.Different wavelet filters can be selected according to different applications. The number of decompositions and data extension can be configured.Moreover,finite precision analysis has been carried out and the bit width of data path is decided.The architecture has been implemented in RTL-Level Verilog. Estimated gates of our processed architecture in SIMC 0.18-μm technology are 6600and the estimated frequency of operation is 300 MHz.The proposed architecture was implemented in Xilinx XC2V2000FPGA.Additionally,comparison was carried out between our architecture and related one,showing that our architecture has better performance in flexibility and maximum processing speed.