Abstract: Because of lacking candidate subgraphs relationship analysis,extended instructions generated by current instruction extension method may not be able to obtain expectable performance improvement.Subgraph relationships are discussed in detail and corresponding instruction set extension algorithm is proposed.During subgraph identification,related subgraphs are combined together under latency constraint and overlapped subgraphs are combined according to the position of overlapped nodes.During subgraph compaction,the performance gain can be adjusted dynamically according to subgraph relationships.Both can eliminate estimation errors effectively.Moreover,this algorithm also makes tradeoff between time cost and precision according to performance gain of left candidate subgraphs.This method has already been implemented in an automatic design flow for TTA based ASIP,with only 0.17% estimation errors on average,far less than the original 3.6%.