Abstract: In this paper, a lumped RLC interconnect tree for gate output is modeled with a simple circuit segment, and the gate load delay is then calculated. Through the representation of the lumped RLC interconnect tree in binary tree structure, the driving point admittance moment may be rapidly obtained, and the parameters R₁, L₁, C₁ and C₂ in the Π model are deduced, then the gate load delay is obtained from ramp response. The simulation result is within 3% deviation from the one obtained with Spice, so the model proves to be feasible in gate delay estimation for design verification.