Abstract: A yield driven clock skew scheduling algorithm is proposed in presence of process variations. Firstly,we present the concept of statistical timing constraint graph and transform a sequential circuit into a statistical timing constraint graph by using the result of statistical timing analysis.Then,the slacks are assigned proportionally in the critical cycles,which are detected iteratively using the algorithm for minimum cost-to-time ratio cycle problem.Experimental results show that the algorithm can help with is improving the yield of integrated circuits.