Abstract: A new methodology based on a deterministically complete test set is proposed．The method described arises from the division of complete test set into several test subsets and each subset corresponds to a weight set．A certain weight set comprises of the probabilities of producing a logic “1” to each primary input of circuits under test． The method provides effective improvement in the test length of test hardware overhead compared with the previously published results ［2-3］，it is suitable for BISTof VLSI especially．