Abstract: Functional verification of complex microprocessor has now been a major bottleneck faced by design communities. To improve the efficiency of functional verification, this paper presents two efficient acceleration techniques: self-verification and co-simulation of mixed model. The former achieves the improvement of verification efficiency by automating the whole verification process over the vector space, and its effect is directly proportional to the number of vectors in the vector space, while inversely proportional to the average vector size. By simulating the system made up of modules at different abstract levels, the second method can reduce the time required to simulate full-chip netlist from exponential to linear relation with the number of integral modules. The validity of the proposed framework has been testified in the verification practice of a 32-bit high-end processor.