Abstract: Timing analysis is an important method for the performance verification of VLSI design. Based on the detailed discussion of the algorithms used for MOS VLSI switch-level timing analysis, two new algorithms, node state assignment algorithm and improved node state assignment algorithm, are proposed to eliminate the false paths. The experimental results of several LSI circuits analyzed by different algorithms show that the new algorithms can very efficiently eliminate false paths with almost no increasing of CPU time and memory compared to the algorithm used in crystal.