高级检索

RTL综合中VHDL算术操作符的综合

VHDL Arithmetic Operator Synthesis in RTL Synthesis

  • 摘要: 寄存器传输级(RTL)综合实现从RTL行为描述到门级结构描述的转换,是目前EDA设计行业的主流设计方法.算术操作符是RTL综合中难于综合的一类操作符,文中详尽解释了IEEE制定的有关算术操作符的各种限制,并对部分算术操作符的限制阐述了自己的观点;分析了各算术操作符的实现方案,并基于电路面积、电路速度,确定了适合RTL综合的实现方案;最后,给出在自行开发的RTL综合工具中进行的算术操作符综合测试,测试表明,所用的各种算术操作符实现方案具有良好的可行性和有效性.

     

    Abstract: As the behavior of digital system can be fully described by the register transfer level (RTL)behavior descriptor,so RTL synthesis has become the mainstream design method in EDA domain.Arithmetic operator is a kind of operators which is very difficult to synthesize in RTL synthesis.In this paper,we analyze all restrictions on arithmetic operators set by IEEE,and set forward our viewpoint on some arithmetic operators.In addition,we give forth implement solutions for each arithmetic operator and underline those solutions which suit RTL synthesis.Fi-nally,the paper presents tests done on the RTL synthesis tool developed by the authors,which show that these implement solutions are feasible and effective.

     

/

返回文章
返回