Abstract: Gate array design methodology depends on a pre-designed gate array base structure. Traditional way to design a base is to write a tedious base description file manually, in which the information of chip scale, channel capacity, core cell, pad cell, modeling of placement and routing, etc., are included. For instance, the Gatemaster of Daisy system adopted this inefficient approach. An antomatical base generator-BaseGen is presented in this paper. According to several crucial parameters, it can generate the base automatically in both layout and topology. It can fit all double metal-layer technology and is design rules independent. BaseGen has been a module of the FELLOW .system1, a CMOS double metal-layer gate array design system.The output of BaseGen can be either layout data with CIF2.0 format or topological data with DLL (Data Listing Language) 2 format. Utilizing BaseGen, three chips, which are 2.5k gates, 4.5K. gates and 6.5K gates respectively' have been designed successfully.