SoC测试中低成本、低功耗的芯核包装方法

Wrapper Design for Low Cost and Low Power in SoC Test

摘要: 提出一种SoC测试中新颖的并行芯核包装方法(parallel core wrapper design,pCWD),该包装方法利用扫描切片重叠这一特点,通过缩短包装扫描链长度来减少测试功耗和测试时间.为了进一步减少测试时间,还提出了一种测试向量扫描切片划分和赋值算法.实验结果表明,针对ITC 2002基准SoC集中d695芯片,应用并行包装方法和测试向量切片划分及赋值算法,能够减少50%的测试时间及95%的测试功耗.

Abstract: A novel parallel core wrapper design (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns.In order to achieve good shift time reduction from overlapping in pCWD,a two-phase process:"partition" and "fill",is presented.Experimental results on d695 of ITC2002benchmark demonstrate that about 50% shift time and 95% test power reduction can be achieved.